Linux-boot.elf binary which is created by petalinux

#LINUX BOOT.ELF BINARY WHICH IS CREATED BY PETALINUX INSTALL#

Petalinux-create -t project вЂ“template zynqMP -n ultra96v2-petalinuxД¤- Go to the generated project folder and configure the project Source /home/opt/petalinux/2019.2/settings.shДЈ- In the вЂњultra96v2-vitis-pkgвЂќ folder create a PetaLinux project ultra96v2.xsa 2- Linux OSДЎ- Go to the вЂњultra96v2-vitis-pkgвЂќ folder generated in the first step (i.e., 1-XSA design) and run the followoing commandsДў- Run the setting.sh file located at the PetaLinux installation folder by running this command Write_hw_platform -include_bit ultra96v2.xsaДў6- You can validate the generated XSA file by running the following TCL command. and run the following TCL command to generate the XSA file Go to вЂњultra96v2-vitis-pkg/vivadoвЂќ that you have created. you can use pwd command to check the folder. And from the popup menu select вЂњCreate HDL WrapperвЂ¦ вЂќ and select the вЂњLet Viviado manage wrapper and auto-updateвЂќ option in the dialog box.Дў5- Then under the PROGRAM AND DEBUG option in the left-hand side panel, select вЂњGenerate BitstreamвЂќ and wait until the end of the process.Дў5- After generating the bitstream, go to the TCL Console view and make sure you are in the right folder. And from the popup menu select вЂњGenerate Output ProductsвЂ¦вЂќ.Дў3- Select the Generate button and wait for the process to finish.Дў4- Again, press the right-click on the вЂњultra96v2_design (ultra96v2_design.bd)вЂќ option in the source view panel. Set_property fault_output_type вЂњsd_cardвЂќ Дў1- Press the right-click in Diagram view and in the popup menu select Validate Design.Дў2- Press the right-click on the вЂњultra96v2_design (ultra96v2_design.bd)вЂќ option in the source view panel. Set_property sign_intent.datacenter false Set_property sign_intent.external_host false Change ids of clk_out2, clk_out3, and clk_out4 to 1, 2, and 3, respectively.ДЎ9- In the xlconcat_0 interfaces, enable In0, Int1, Int2, Int3, Int4, Int5, Int6, Int7, which are interrupt interfaces.Дў0- Go to the вЂњTCL ConsoleвЂќ view and run these commands Note, to change the id filed you must press the Enter key on your keyboard. (WindowвЂ“>Platform Interfaces).ДЎ5- Click on вЂњEnable platform interfacesвЂќ if this the first time you select the Platform Interfaces option in the project.ДЎ6- By write click on each option and select Enable to enable the following interfaces:ДЎ7- Enable the following clock interfacesДЎ8- Select the enabled clk_out1 and in the Options window change the id to 0 and select the is_default. For this purpose, select вЂњPlatform InterfacesвЂќ option from the вЂњWindowвЂќ menu in the Vivado IDE.

Figure 16 Figure 17ДЎ4- Now, we should declare the platform (PFM) interface and properties. Figure 14ДЎ3- Configure the added IP as Figure 16 and connect that to the Zynq as shown in Figure 7. Figure 13ДЎ1- Add connections as Figure 14. Figure 12ДЎ0- Add four Processor System Reset IPs corresponding to four output clocks.

Add four output clocks and make sure that the reset type is вЂњActive LowвЂќ. Figure 11Д©- Double click on the added IP and configure that as Figure 12. Figure 9Д§- Double click on the Zynq IP and configure that as Figure ? Figure 10ДЁ- Add a Clocking Wizard IP to the design. Figure 7ДҐ- Add a Zynq UltraScale+ MPSoC IP into the Diagram view Figure 8Д¦- Click on вЂњRun Block AutomationвЂќ and make sure the вЂњApply Board ResetвЂќ is selected. Figure 1 Figure 2 Figure 3 Figure 4 Figure 5 Figure 6Д¤- In the Vivado project, create a block design with the name ultra96v2_design. Figures 1-6 show the flow of the project creation. 1- XSA designДЎ- create a directory called ultra96v2-vitis-pkgДЈ- Run Vivado and create a project called ultra96v2-xsa in the ultra96v2-vitis-pkg/vivado folder. To make Vivado detects the board, copy the Avnet ultra96v2 board definition files (at here) to the /data/boards/board_files.

#LINUX BOOT.ELF BINARY WHICH IS CREATED BY PETALINUX INSTALL#

Note that, the Xilinx Vitis software includes Vivado, so you do not need to install that separately. I have installed Xilinx Vitis and Petalinux 2019.2 under the Ubuntu 18.04 OS. In the sequel, I am trying to briefly explain each step. TestвЂ“ Create a simple application to test the generated platform.Create Platform вЂ“ Using Xilinx Vitis to generate the Platform.Linux OS вЂ“ Generating a PetaLinux project to configure Linux.XSA design вЂ“ Generating a Vivado project containing the underlying hardware.Creating the Ulra96v2 platform in the Xilinx Vitis has four steps:

Linux-boot.elf binary which is created by petalinux